In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that (1) would limit the resolution of photo-lithography and creation of dense feature patterns, and (2) would lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the end-point can be difficult to detect. They are also expensive. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of low-k dielectrics into chip production, modification of traditional CMP processes will be required, as current methods result in cracking and delamination of most low-k materials, which have a very low compression strength, and are extremely fragile.
Another method of planarization involves electrolytic etching technique such as electropolishing or electroless etching. These techniques are low cost methods, relative to CMP. Lower capital cost, easier waste handling, and much higher processing rates make it a desirable alternative to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. The process may be viewed as the reverse of electroplating.
A problem arises during the electropolishing of surfaces in which a large number of low aspect ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low aspect ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the Damascene layer so that the feature will be completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles which resemble the original (low aspect ratio) feature. The metallization processes used to deposit the metal, which are substantially conformal over such low aspect ratio features, are typically not continued to a point which would geometrically “close” such recesses, because to do so would require depositing a very thick metal layer. To do so would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low aspect ratio features are propagated and expanded to produce recesses that span the width of these features leaving effectively little or no metal in the pad regions. Obviously, this is an unacceptable result.
The current state of electropolishing technology has additional difficulties. For example, electropolishing typically requires highly viscous electrolyte baths (e.g., 85% phosphoric acid (H3PO4) in water, or with some added ethylene glycol). While these baths are effective in achieving good polishing and planarization rates, they make it difficult to remove defect-causing bubbles and to handle the fluids in general. Note that, depending on the electrolyte and tool design, a hydrogen generating reaction may take place at the cathode. The hydrogen can become entrained in the electrolyte, complicating tool design and presenting a potential safety hazard. In addition, these baths also have high resistivities, making for large power requirements and substantial amounts of generated heat (which must be removed to maintain a constant process control).
Mayer et. al. (U.S. patent application Ser. No. 09/412,837, filed Oct. 5, 1999) describe a method of planarization of metal surfaces on wafers having both large and small recessed features by applying a film to the wafer surface prior to electropolishing. This film is applied in such a way that the film is thicker in the large feature recessed regions, and thinner over the substantially flat regions, and thinnest on exposed regions. This method allows differential electropolishing rates on different areas of the wafer such that planarization is achieved. While this technique is more effective with respect to conventional electropolishing approaches, the added application step can add cost to the operation, and may not sufficiently address planarization of raised regions (bumps) on the metal surface.
As mentioned, electroplating is a process that generally yields conformal deposition over low aspect ratio features and for the reasons described above, electroplating typically leaves large recessed areas over these type features. Additionally, it can be shown for conventional copper plating baths (i.e. not “superfilling” baths) both theoretically and experimentally that high aspect ratio features (i.e. depth to width >3:1) are rapidly filled, and the metal above them becomes rapidly planarized. Using the electroplating methods mentioned above, small recessed areas exist in the metal fill profile over high aspect ratio features.
More commonly today however, electroplating bath additives are utilized to aid in the rapid “bottom-up” filling of higher aspect ratio features (e.g. in Damascene copper electroplating processes) to ensure homogeneous metal fill of these narrow features. Baths with “bottom-up” filling characteristics planarize smaller features much more rapidly than baths without such additives. In some cases (e.g. plating baths with superior bottom-up filling characteristic and no leveling additives) plating occurs at an accelerated rate after completing the small feature filling stage (see for example, “A Superfilling Model that Predicts Bump Formation”, A. C. West, S. Mayer, and J. Reid, Electrochemical and Solid State Letters, Vol. 4, No. 7, July 2001 and “Integration of Copper PVD and Electroplating Process for Damascence Feature Electrofilling, S. Mayer et. al., Interconnects and Contact Metalization for ULSI, Proceeding of the International Symposium, Electrochemical Society Inc., Volume 99-31, and “Factors Influencing Damascene Feature Fill Using Copper PVD and Electroplating”, Solid State Technology, July, 2000, pg 86-103). When many high aspect ratio features are located in close proximity, a macroscopic raised area (series of bumps or a raised plateau) can be formed. This bump formation is also termed, “feature overplating.”
Thus, use of advanced “bottom up” electrofill paradigms in combination with wafers having many low and high aspect features have created a problem of deposited metal surfaces having a range of topography to be planarized that is unusually large, i.e. containing both recessed and raised areas. Commonly, features that vary in size by two orders of magnitude on a single layer exist. A 1 μm deep feature can have widths of from 0.2 μm to 100 μm. Therefore, while electroplating is a preferred method of metalization, various aspects of improved plating regimens create challenging topography for subsequent planarization.
What is needed therefore is improved electropolishing, electroetching and chemical etching technology for planarizing conductive layers having varying topography, particularly conductive layers having both recesses and raised regions having both very small (submicron) and very large (on the order of 100 micron) widths.